Journal of Advances in Developmental Research

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A Widely Indexed Open Access Peer Reviewed Multidisciplinary Bi-monthly Scholarly International Journal

Call for Paper Volume 16 Issue 2 July-December 2025 Submit your research before last 3 days of December to publish your research paper in the issue of July-December.

Designing Neural-Network Accelerators Using RISC-V Architectures

Author(s) Karthik Wali
Country United States
Abstract The proliferation of deep learning applications has necessitated the development of specialized hardware accelerators to meet the computational demands of neural networks. RISC-V, an open-source instruction set architecture (ISA), offers a flexible and extensible platform for designing such accelerators. This paper explores the integration of neural-network accelerators within RISC-V architectures, analyzing design methodologies, performance metrics, and energy efficiency. Through a comprehensive literature review and methodological analysis, we highlight the potential of RISC-V in advancing neural-network acceleration and discuss future directions in this domain.
The significance of RISC-V lies not only in its openness but also in its support for customizable extensions, which makes it an ideal platform for tailoring hardware to the specific requirements of neural networks. Neural workloads are characterized by high parallelism, intensive matrix computations, and increasing demands for real-time inference in constrained environments. RISC-V enables hardware designers to co-optimize both performance and power through domain-specific enhancements while maintaining architectural simplicity.
This paper also presents key performance metrics from existing RISC-V-based neural accelerators and provides insights into instruction set extensions, hardware-software co-design strategies, and the role of microarchitectural innovations. The flexibility of RISC-V could play a pivotal role in democratizing AI hardware and enabling innovation across industry, academia, and edge computing domains.
Field Engineering
Published In Volume 14, Issue 2, July-December 2023
Published On 2023-10-06
Cite This Designing Neural-Network Accelerators Using RISC-V Architectures - Karthik Wali - IJAIDR Volume 14, Issue 2, July-December 2023. DOI 10.71097/IJAIDR.v14.i2.1467
DOI https://doi.org/10.71097/IJAIDR.v14.i2.1467
Short DOI https://doi.org/g9q342

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